If random variations of transistor increase with the progress of scaling in a semiconductor storage device, variations of a cell current to charge/discharge a bit line become noticeable. With variations of the cell current, a delay (bit line delay) until a desired potential difference appears in a pair of bit lines after the voltage of a word line rises also varies. Activation timing of a sense amplifier or inactivation timing of a word line attendant thereon in a memory is normally generated by a timing generator. However, according to this method, timing variations due to random variations of transistor generally cannot be accurately replicated. Thus, functionality is guaranteed by setting the timing considered to be the worst case. However, this method requires unnecessary timing margins, causing lower operating frequencies or increased power consumption.
Moreover, according to such a way of securing timing margins, fluctuations of optimum timing caused by changes of random variations or fluctuations of power supply voltage cannot be replicated satisfactorily.